Circuit for avoiding false lock

ABSTRACT

It is well known that the autocorrelation function of a psuedorandom sequence, multiplied by itself delayed, theoretically consists of one peak at zero delay and approximately zero amplitude at all other delays. It is also known that, in practice, there are second order effects which give rise to secondary peaks at delays other than zero. In a system such a pseudo-randomly phase modulated radar altimeter, which utilizes the autocorrelation peak to lock on and track, the appearance of secondary peaks may cause false locks. The instant invention is directed at means for avoiding false locks, and comprises means for altering the pseudo-random sequences of the modulating code generator and the tracking code generator at a predetermined rate. The timing of the alteration is such that the sequence of the modulating code generator will be altered only when there exists in the modulating code generator a predetermined word, e.g., the all ones state. The sequence of the tracking code generator is altered the first time that the same predetermined word exists in the tracking code generator after the sequence of the modulating code generator has been altered.

United States Patent 1 91 Matthews 1- Apr. 17, 1973 CIRCUIT FOR AVOIDINGFALSE LOCK [75] Inventor: Solomon Bertram Matthews, Montreal, Quebec,Canada [73] Assignee: Canadian Marconi Company, Montreal, Quebec, Canada22 Filed: Aug. 16,1971

211 Appl.No.: 171,971

343/172 R, 17.2 PC; 235/181 [56] References Cited UNITED STATES PATENTS3,663,935 5/1972 MacMullen ..343/l7.2 R

Primary Examiner-T. H. Tubbesing Attorney-Melvin Sher [5 7] ABSTRACT Itis well known that the autocorrelation function of a psuedo-randomsequence, multiplied by itself delayed, theoretically consists of onepeak at zero delay and approximately zero amplitude at all other delays.It is also known that, in practice, there are second order effects whichgive rise to secondary peaks at delays other than zero. In a system sucha pseudo-randomly phase modulated radar altimeter, which utilizes theautocorrelation peak to lock on and track, the appearance of secondarypeaks may cause false locks. The instant invention is directed at meansfor avoiding false locks, and comprises means for altering thepseudo-random sequences of the modulating code generator and thetracking code generator at a predetermined rate. The timing of thealteration is such that the sequence of the modulating code generatorwill be altered only when there exists in the modulating code generatora predetermined word, e.g., the all ones state. The sequence of thetracking code generator is altered the first time that the samepredetermined word exists in the tracking code generator after thesequence of the modulating code generator has been altered.

4 Claims, 3 Drawing Figures TX OUTPUT CODE SEQUENCE AND GATE FEEDBACKSELECTOR LOGIC CCT RX OUTPU COOE SEQUENCE FEEDBACK SELECTOR LOGIC CCTTIME SHARING PULSES LOGIC 5 SQUARE WAVE INPUT L RX SYNC PULSES PATENTED3.728.533

TX OUTPUT coo: 12a4ss1s9|on SEQUENCE 4 I 3 AND FEEDBACK GATE SELECTORLOGIC OCT PC DUAL'DF/F RX OUTPUT |]2]3|4|5[sl1|a|9||o coos V sequenceFEEDBACK SELECTOR LOGIC ccT RX smc PULSES 8 TIME SHARING 9 SYNC PULSEFIGURE 2 TX SYNC GENERATOR V PULSES LOGIC SQUAISIEU'IV'IAVE FIGURE I0Q--. MODULO 2 ADDERS, IE

CIRCUIT FOR AVOIDING FALSE LOCK This invention relates to a method foravoiding false locks in a self-contained echo type range measuringsystem which measures the time delay between a transmitted signal andits echo wherein the transmitted signal is a pseudo-randomly modulatedsignal and the delay measurement is made by cross correlating thetransmitted signal with a received echo signal, and to apparatus forcarrying out the method.

Such systems may comprise pseudo-randomly phase modulated radaraltimeters, laser range finders, intrusion detection radars, sonars,etc. The modulation may be phase modulation, frequency modulation,and/or amplitude modulation, just so long as it is pseudo-random anddelay cross correlation tracking is used. However, the disclosure willbe restricted to a discussion concerning only the pseudo-randomly phasemodulated radar altimeter.

It is well known that the autocorrelation function of a pseudo-randomsequence theoretically consists of one peak at zero delay andapproximately zero amplitude at all other delays. (See, for example,page 6 of DRTE Report No. 1031 by Davies, N.G., titled Some Propertiesof Linear Recursive Sequences" dated December 1959.). It is equally wellknown that, in practice, there are second order effects which give riseto small peaks in the autocorrelation function at delays other thanzero. These second order peaks may be caused either by ground returns orleaks between transmitter and receiver, and although they are typicallyof the order of 30 db to 80 db below the main autocorrelation peak, theymay nevertheless cause false locks in a system such as described in ourcopending US. Pat. application Ser. No. 172,071 filed Aug. 16, 1971.

It is, therefore, an object of the invention to provide a circuit forthe avoidance of false locks as above described.

The invention will be understood by examination of the followingdescription together with the accompanying drawings in which:

FIGS. la and 1b illustrate two different feedback connections which maybe used to derive a pseudo-random sequence with an I 1 stage shiftregister; and

FIG. 2 illustrates a circuit which comprises one embodiment of theinvention.

It is well known that pseudo-noise (pseudo-random) sequences may beproduced by a shift register with appropriate feedback connections. (Seefor example, Electron Technology, October 1960, page 389 et seq, ShiftRegisters, Scholfield, or IEEE Transactions on Communication Technology,Vol. COM-l3, No. 4, December I965, page 475 et seq, Acquisition ofPseudonoise Signals by Sequential Estimation, Ward.)

FIGS. la and lb illustrate two feedback connections for producingmaximal length pseudo-random sequences from an 1'] stage shift register.In FIG. 1a and lb, I-I I represent the flip-flops in an I 1 stage shiftregister and 100 represents modulo 2 adders, i.e. EX- CLUSIVE OR gates.In FIG. 1a, the feedback connec tions are from stages 6, 8, 9 and II andin FIG. 1b the feedback connections are from stages 6, 8, l and 11. Asis well known, other feedback connections will produce a pseudo-randomsequence from an 11 stage register, nor is the number of feedback tapsrestricted to four, or the number of stages restricted to 11. However,although different feedback connections will produce pseudo-randomsequences having the same autocorrelation function, the sequencesproduced by the different arrangements will be different, i.e., thespecific times of appearance of ones and zeroes will be different forthe different arrangements although the ones and zeroes in botharrangements will appear in a pseudo-random fashion.

Secondary peaks will be produced no matter which feedback connectionsare used; however, these secondary peaks will occur at differentpositions relative to the zero delay peaks. The autocorrelation functionof the sequence, however, is not a function of the feedback connections,but only of the number of stages in the sequence producing shiftregister, so long as the feedback connections produce a pseudo-randomsequence.

This phenomenon can be used to detect false locks as follows: thefeedback connections of the sequence producing shift register areperiodically altered, for example, as between two or more differentsequences. If, while the register is in one feedback position, thesystem locks onto a secondary peak, then when the feedback connection isaltered, there will no longer be a secondary peak in the same relativeposition so that the system WiIIIIO longer be locked. If, however, thesystem is locked onto the primary (zero delay) peak, when the feedbackconnections are altered, the primary peak will remain in the samerelative position so that the system will remain locked onto this peak.

It can be seen that, by providing means for altering the feedbackconnections in the sequence producing shift registers, a means isprovided for detecting false locks.

However, a critical point is the time at which the feedback connectionsare switched. It is, of course, well known that in a system such asdescribed in our copending US. application Ser. No. 172,071, both amodulating (transmitter) code generator and a tracking (receiver) codegenerator are required. In order to effect the instant invention, it isnecessary to alter the sequences of both generators in such a way thatthe feedback connections of both generators become the same. However, itcan be shown that both generators cannot have their sequences changed atthe exact same time without providing a circuit which determines binarywords corresponding to particular delays. This effect can be explainedas follows: if we consider a modulating and tracking code generator atone instant in time, then the modulating code generator will have abinary word which we will call b and the tracking code generator willhave a binary word which we will call 12 Assuming the system istracking, the delay between b and b is D where D corresponds to thealtitude delay, ie at this particular altitude, and with this particularclocking pulse rate, and with this particular sequence, the binary wordb will appear D time units after the appearance of b If the feedbackconnections were to be altered at this moment in time, the binary wordsin both registers would be unchanged immediately after the alterationtook place. However, because the sequences have been changed, the delaybetween b and b is no longer D but some other delay D i.e., the trackingcode generator is now delayed from the modulating code generator by adelay D different than D Thus, the system would no longer be tracking,and it would be necessary for the system to reacquire.

It has been discovered that if the sequences are altered when apredetermined word, e.g., the all ones state, exists in the generators,in such a manner that the feedback connections of the modulating codegenerator are switched when that word exists in the modulating codegenerator and the feedback connections of the tracking code generatorare switched, not at that same instant of time, but at the timeimmediately following the switching of the modulating code generator,when the predetermined word exists in the tracking code generator, thenthe delay between the binary words in the generators will not be alteredby the switching ac- ;tion. It will, of course, be appreciated that thefeedback connections will not be changed every time the predeterminedbinary word appears, but that they will be changed at a predeterminedrate synchronized by the predetermined binary words.

FIG. 2 illustrates one circuit for implementing the above action. InFIG. 2, l and are 11 stage shift registers and 2 and are modulo addersthrough which feedback connections are effected in registers 1 and 10respectively. As can be seen, the feedback connections are from stage 6,8, 9 and 11 or 6, 8, l0 and 11 depending on the states of the feedbackselector logic circuits 3 and 30. The output terminals of each stage ofthe registers are fed to the input terminals of ll-input AND gates 4 and40, and the outputs of the AND gates are fed to two separate inputs oftime sharing sync pulse generator 5.

The generator 5 has a square wave applied at a further input terminalthereof and provides, on its output line 8, the first output pulse ofAND gate 4 after the input square wave has changed sign and, on theoutput line 9, the first output pulse of AND gate 40 after the inputsquare wave has changed sign. In this way, clock pulses are provided toD flip-flop 6 at the input square wave rate, but synchronized to theoccurrence of the all ones state of shift register 1. In a like manner,clock pulses are provided to D flip-flop 7 at the input square wave rateand synchronized to the occurrence of the all ones state in shiftregister 10. (The D flip-flop is a .I-K flip-flop with the J and Kterminals connected.) The feedback connection selected by the circuits 3and 30 is a function of the state of the signal applied to the circuits3 and 30 at their control terminals from the Q terminals of the Dflip-flops.

In operation, when a clock pulse is applied to flipflop 6, the Qterminal will assume the state of the D terminal. Simultaneously, inview of the fact that the Q terminal is of the opposite state to the Qterminal, and in view of the fact that the Q terminal is connected tothe D terminal, the D terminal will change states. This ensures that theQ terminal alternates states on alternate clock pulses.

The O terminal of the flip-flop 7 follows the output of the Q terminalwith a delay equal to the delay between the all ones state of themodulating code generator and the all ones state of the tracking codegenerator.

Thus it can be seen that the feedback connections of the generators willbe changed at a predetermined rate and only when a predetermined word(the all ones state) exists in the generators, and that the feedbackconnections of the modulating code generator will be changed before thefeedback connections of the tracking code generator are changed.

Although a specific embodiment has been described above, it isunderstood that this was for the purpose of illustrating, but notlimiting, the invention. Various modifications which will come readilyto the mind of one skilled in the art are considered to be within thescope of the invention as defined in the appended claims.

I claim:

1. In a system comprising two generators for producing identicalpseudo-random sequences of a given length; said generators eachcomprising a shift register having a plurality of stages and a set offeedback connections from a number of said stages through modulo 2adders to the input stage of the shift register; said generators beingadapted to produce a different pseudo-random sequence of the same lengthwhen said feedback connections are appropriately altered; means foraltering said feedback connections of one of said generators to producesaid different pseudo-random sequence when a predetermined binary wordexists in said one generator; and means for altering the feedbackconnections of the other one of said generators to produce saiddifferent pseudo-random sequence after said feedback connections havebeen altered in said one generator and when said predetermined binaryword exists in said other generator.

2. A system as defined in claim 1 wherein said means for altering thefeedback connections of said one generator are further adapted to returnsaid feedback connections to said set of feedback connections after apredetermined time and when said predetermined binary word exists insaid one generator and the feedback connections comprise said alteredfeedback connections; and wherein the means for altering the feedbackconnections of said other generator are further adapted to return saidfeedback connections to said set of feedback connections after apredetermined time and when said predetermined binary word exists insaid other generator and the feedback connections comprise said alteredfeedback connections.

3. A system as defined in claim 2 wherein said first generator compriseseleven serially connected flipflops, each flip-flop comprising an inputterminal and an output terminal; and further comprising three modulo 2adders, each adder comprising two input ter-' minals and an outputterminal; and feedback selector logic means comprising two inputterminals, an output terminal, and a control terminal; the outputterminals of said sixth and eighth flip-flops being connectedrespectively to the first and second input terminals of one of saidmodulo 2 adders; the output terminals of said ninth and tenth flip-flopsbeing connected respectively to the first and second input terminals ofsaid feedback selector logic means; the output terminal of the eleventhflip-flop being connected to one input terminal of a second modulo 2adder, and the output terminal of said feedback selector logic meansbeing connected to the second input terminal of said second modulo 2adder; the output terminals of said first and second modulo 2 addersbeing connected respectively to the first and second input terminals ofsaid third modulo 2 adder, the output terminal of said third modulo 2adder being connected to the input terminal of the first flip-flop; andthe control terminal of said feedback selector logic means beingconnected to means for detecting said predetermined binary word in saidfirst generator; wherein said feedback selector logic means comprisessaid means for altering the feedback connections of said one generator;whereby said feedback connections of said one generator alternatebetween feedback from sixth, eighth, ninth and eleventh flip-flop outputterminals and feedback from said sixth, eighth, tenth and eleventhflip-flop output terminals; and wherein said second generator comprisesa further eleven serially connected flip-flops, each further flip-flopcomprising an input terminal and an output terminal; and furthercomprising three further modulo 2 adders, each further adder comprisingtwo input terminals and an output terminal; and a further feedbackselector logic means comprising two input terminals, an output terminaland a control terminal; the output terminals of said further sixth andeighth flip-flops being connected respectively to the first and secondinput terminals of one of said further modulo 2 adders; the outputterminals of said further ninth and tenth flip-flops being connectedrespectively to the first and second input terminals of said furtherfeedback selector logic means; the output terminal of the furthereleventh flip-flop being connected to one input terminal of a secondfurther modulo 2 adder, and the output terminal of said further feedbackselector logic means being connected to the second input terminal ofsaid further second modulo 2 adder; the output terminals of said furtherfirst and second modulo 2 adders being connected respectively to thefirst and second input terminals of said further third modulo 2 adder,the output terminal of said further third modulo 2 adder being connectedto the input terminal of the further first flip-flop; and the controlterminal of said further feedback selector logic means being connectedto further means for detecting said predetermined word in said secondgenerator; wherein said further feedback selector logic means comprisessaid means for altering the feedback connections of said secondgenerator; whereby said feedback connections of said second generatoralternate between feedback from said sixth, eighth, ninth and eleventhflipflop output terminals and feedback from said sixth, eighth, tenthand eleventh flip-flop output terminals.

4. A system as defined in claim 3 wherein said means for detecting saidpredetermined binary word in said first generator comprises a first ll-input AND gate, the output terminals of each of said eleven flip-flopsbeing connected respectively to a different input of said AND gate; andwherein said means for detecting said predetermined binary word in saidsecond generator comprises a second 1 l-input AND gate, the outputterminals of each of said further eleven flip-flops being connectedrespectively to a different input of said second AND gate; and furthercomprising a time sharing sync pulse generator having three inputterminals and two output terminals; and two D flip-flops, each having aD input terminal and a clock pulse input terminal, and Q and Q outputterminals; the output terminals of said first and second AND gates beingconnected respectively to the first and second input terminals of saidtime sharing sync pulse generator; and a source of square waves beingconnected to the third input terminal of said time sharing sync pulsegenerator; one output terminal of said sync pulse generator beingconnected to the clock pulse terminal of one of said D flip-flops, theother output terminal of said sync pulse generator being connected tothe clock pulse terminal of said other D flip-flop; the Q outputterminal of said first D flip-fiop being connected to the controlterminal of said feedback selector logic means and the Q output terminalof said second D flip-flop being connected to the control terminal ofsaid further feedback selector logic means, the Q output terminal ofsaid first D flip-flop being connected to the D input terminal of saidfirst D flip-flop, and the Q output terminal of said first D flip-flopbeing further connected to the D input terminal of said second Dflip-flop; whereby clock pulses at said square wave rate andsynchronized with the output of said first AND gate are provided to theclock pulse input terminal of said first D flip-flop; and clock pulsesat said square wave rate and synchronized with the output of said secondAND gate are provided to the clock pulse input terminal of said second Dflip-flop.

1. In a system comprising two generators for producing identicalpseudo-random sequences of a given length; said generators eachcomprising a shift register having a plurality of stages and a set offeedback connections from a number of said stages through modulo 2adders to the input stage of the shift register; said generators beingadapted to produce a different pseudo-random sequence of the same lengthwhen said feedback connections are appropriately altered; means foraltering said feedback connections of one of said generators to producesaid different pseudo-random sequence when a predetermined binary wordexists in said one generator; and means for altering the feedbackconnections of the other one of said generators to produce saiddifferent pseudo-random sequence after said feedback connections havebeen altered in said one generator and when said predetermined binaryword exists in said other generator.
 2. A system as defined in claim 1wherein said means for altering the feedback connections of said onegenerator are further adapted to return said feedback connections tosaid set of feedback connections after a predetermined time and whensaid predetermined binary word exists in said one generator and thefeedback connections comprise said altered feedback connections; andwherein the means for altering the feedback connections of said othergenerator are further adapted to return said feedback connections tosaid set of feedback connections after a predetermined time and whensaid predetermined binary word exists in said other generator and thefeedback connections comprise said altered feedback connections.
 3. Asystem as defined in claim 2 wherein said first generator compriseseleven serially connected flip-flops, each flip-flop comprising an inputterminal and an output terminal; and further comprising three modulo 2adders, each adder comprising two input terminals and an outputterminal; and feedback selector logic means comprising two inputterminals, an output terminal, and a control terminal; the outputterminals of said sixth and eighth flip-flops being connectedrespectively to the first and second input terminals of one of saidmodulo 2 adders; the output terminals of said ninth and tenth flip-flopsbeing connected respectively to the first and second input terminals ofsaid feedback selector logic means; the output terminal of the eleventhflip-flop being connected to one input terminal of a second modulo 2adder, and the output terminal of said feedback selector logic meansbeing connected to the second input terminal of said second modulo 2adder; the output terminals of said first and second modulo 2 addersbeing connected respectively to the first and second input terminals ofsaid third modulo 2 adder, the output terminal of said third modulo 2adder being connected to the input terminal of the first flip-flop; andthe control terminal of said feedback selector logic means beingconnected to means for detecting said predetermined binary word in saidfirst generator; wherein said feedback selector logic means comprisessaid means for altering the feedback connections of said one generator;whereby said feedback connections of said one generator alternatebetween feedback from sixth, eighth, ninth and eleventh flip-flop outputterminals and feedback from said sixth, eighth, tenth and eleventhflip-flop output terminals; and wherein sAid second generator comprisesa further eleven serially connected flip-flops, each further flip-flopcomprising an input terminal and an output terminal; and furthercomprising three further modulo 2 adders, each further adder comprisingtwo input terminals and an output terminal; and a further feedbackselector logic means comprising two input terminals, an output terminaland a control terminal; the output terminals of said further sixth andeighth flip-flops being connected respectively to the first and secondinput terminals of one of said further modulo 2 adders; the outputterminals of said further ninth and tenth flip-flops being connectedrespectively to the first and second input terminals of said furtherfeedback selector logic means; the output terminal of the furthereleventh flip-flop being connected to one input terminal of a secondfurther modulo 2 adder, and the output terminal of said further feedbackselector logic means being connected to the second input terminal ofsaid further second modulo 2 adder; the output terminals of said furtherfirst and second modulo 2 adders being connected respectively to thefirst and second input terminals of said further third modulo 2 adder,the output terminal of said further third modulo 2 adder being connectedto the input terminal of the further first flip-flop; and the controlterminal of said further feedback selector logic means being connectedto further means for detecting said predetermined word in said secondgenerator; wherein said further feedback selector logic means comprisessaid means for altering the feedback connections of said secondgenerator; whereby said feedback connections of said second generatoralternate between feedback from said sixth, eighth, ninth and eleventhflip-flop output terminals and feedback from said sixth, eighth, tenthand eleventh flip-flop output terminals.
 4. A system as defined in claim3 wherein said means for detecting said predetermined binary word insaid first generator comprises a first 11-input AND gate, the outputterminals of each of said eleven flip-flops being connected respectivelyto a different input of said AND gate; and wherein said means fordetecting said predetermined binary word in said second generatorcomprises a second 11-input AND gate, the output terminals of each ofsaid further eleven flip-flops being connected respectively to adifferent input of said second AND gate; and further comprising a timesharing sync pulse generator having three input terminals and two outputterminals; and two D flip-flops, each having a D input terminal and aclock pulse input terminal, and Q and Q output terminals; the outputterminals of said first and second AND gates being connectedrespectively to the first and second input terminals of said timesharing sync pulse generator; and a source of square waves beingconnected to the third input terminal of said time sharing sync pulsegenerator; one output terminal of said sync pulse generator beingconnected to the clock pulse terminal of one of said D flip-flops, theother output terminal of said sync pulse generator being connected tothe clock pulse terminal of said other D flip-flop; the Q outputterminal of said first D flip-flop being connected to the controlterminal of said feedback selector logic means and the Q output terminalof said second D flip-flop being connected to the control terminal ofsaid further feedback selector logic means, the Q output terminal ofsaid first D flip-flop being connected to the D input terminal of saidfirst D flip-flop, and the Q output terminal of said first D flip-flopbeing further connected to the D input terminal of said second Dflip-flop; whereby clock pulses at said square wave rate andsynchronized with the output of said first AND gate are provided to theclock pulse input terminal of said first D flip-flop; and clock pulsesat said square wave rate and synchronized witH the output of said secondAND gate are provided to the clock pulse input terminal of said second Dflip-flop.